1. Field of the Invention
The present invention relates to output drivers and, more particularly, to a low ground bounce and low power supply bounce output driver.
2. Description of the Related Art
A CMOS digital output driver is a well known circuit that outputs a logic high or a logic low to a load capacitance by charging or discharging the load capacitance. In practice, several output drivers are often connected to the same ground (GND) line and the same power supply (VCC) line.
One of the problems associated with connecting several noisy (high di/dt) output drivers to the same ground line is that significant ground bounce (switching noise) can be generated when many (or all) of these output drivers discharge their load capacitances at the same time.
FIG. 1 shows a circuit diagram that illustrates a portion of a conventional output driver circuit 100. As shown in FIG. 1, driver circuit 100 includes a series of high di/dt output drivers driver#1-driver#N which each have a p-channel transistor 110 and an n-channel transistor 112.
Each p-channel transistor 110 has a source connected to a power supply VCC, a drain connected to an output pad 114, and a gate. Each n-channel transistor 112 has a source connected to a common ground line 116, a drain connected to the drain of the p-channel transistor 110, and a gate.
During normal operation, when a single output driver is switched from a logic high to a logic low, a time varying current i(t).sub.D from the load capacitance is placed on common ground line 116 as a result of the load capacitance being discharged. Similarly, when all of the output drivers driver#1-driver#N are simultaneously switched from a logic high to a logic low, a large time varying discharge current, which is the sum of the individual time varying discharge currents i(t).sub.D, is placed on common ground line 116.
The large time varying discharge current causes the voltage on common ground line 116 to vary due to the inductance of common ground line 116 (which is shown as an inductor L). As shown in EQ. 1, the voltage variation VLG on common ground line 116 is defined as follows: EQU VLG=L*N(di(t)/dt) EQ. 1
where L represents the inductance of common ground line 116 (including package inductance and bondwire inductance), N represents the number of drivers driver#1-driver#N that are discharging their load capacitances at the same time, and di(t)/dt represents the time varying discharge current i(t).sub.D through a single driver.
Thus, as shown in EQ. 1, extremely high ground bounce (switching noise) can be generated when several drivers driver#1-driver#N are switched from a logic high to a logic low at the same time.
Similarly, a significant power supply bounce (switching noise) can be generated when several noisy (high di/dt) output drivers charge their load capacitances from the same power supply line at the same time.
FIG. 2 shows a circuit diagram that illustrates a portion of a conventional output driver circuit 200. Output driver circuit 200 is similar to output driver circuit 100 and, as a result, utilizes the same reference numerals to designate the structures which are common to both circuits.
In addition to the elements of circuit 100, output driver circuit 200 also includes a common power supply line 210 which is connected to the source of the p-channel transistor 110 in each of the output drivers driver#1-driver#N.
During normal operation, when a single output driver is switched from a logic low to a logic high, a time varying charge current i(t).sub.c from the VCC power supply is placed on common power supply line 210, as a result of the load capacitance being charged. Similarly, when all of the output drivers driver#1-driver#N are simultaneously switched from a logic low to a logic high, a large time varying charge current from the VCC power supply is placed on common power supply line 210. This time varying current is the sum of the individual time varying charge currents i(t).sub.c.
The large time varying current causes the voltage on common power supply line 210 to also vary due to the inductance of line 210 (shown as inductor L). As shown in EQ. 2, the voltage variation VLV on common power supply line 210 is defined as follows: EQU VLV=L*N(di(t)/dt) EQ. 2
where L represents the inductance of power supply line 210 (including package inductance and bondwire inductance), N represents the number of drivers driver#1-driver#N that are charging their load capacitances at the same time, and di(t)/dt represents a single time varying charge current i(t).sub.c.
Thus, as shown in EQ. 2, extremely high power supply bounce (switching noise) can be generated when several drivers driver#1-driver#N are switched from a logic low to a logic high at the same time.
Thus, in view of the above discussion, there is a need for an output driver that can minimize the ground bounce and power supply bounce that can occur when several high di/dt output drivers discharge or charge their load capacitances at the same time.